1. Field of the Invention
The present invention relates to a radio receiving apparatus for receiving radio-transmitted digital data, and in particular to a paging receiver which provides digital data receiving and display functions, with the receiver having a data communication protocol analysis function.
2. Description of the Prior Art
By comparison with wired (i.e. cable-connected) digital data transmission, radio transmission of digital data is highly susceptible to externally induced noise. Because of this, and also because in general the effective data transmission rate is relatively low, radio data transmission has hitherto been used for transferring only small amounts of data at a time. In particular in the case of a radio paging system, since each paging receiver is extremely small in size, the receivers have been generally limited to displaying an array of approximately twenty to thirty numerals or characters. However due to changes which have occurred in recent years with regard to increased efficiency of modulation techniques and the development of communication protocols which are highly effective against the effects of noise, it has become feasible to transfer digital data at a high transmission rate via radio. Thus for example in the case of a paging system, it has become technically possible to transmit large sections of text, or images, etc., which are expressed by large amounts of data.
In the case of a communication protocol which makes possible such high-speed transmission of data by radio, the protocol itself is extremely complex, and as a result the paging receiver must incorporate a function for analyzing the protocol. For example with one method, to reduce the effects of induced noise, the transmitted digital data are encoded using a BCH (Bose Chaudhuri Hocquenghem) code, with the resultant data being interleaved and transmitted. In that case, the paging receiver must incorporate a function for analyzing the interleaved encoded data, and executing decoding of the BCH code to achieve error correction. The BCH code error correction method is also known as the "polynomial code" method, or "cyclic redundancy code (CRC)" method.
There are two possible approaches for implementing such a function. With one approach, dedicated hardware is provided in the paging receiver. With the other method, a software implementation is used, i.e. a suitable program is executed by the paging receiver for analyzing the communication protocol. Use of the first of these two possible approaches, with a prior art paging receiver, will first be described. FIG. 27 is a general system block diagram of an example of such a prior art paging receiver. In FIG. 27, a ROM (Read-only Memory) 2601 stores a program that is executed by a CPU 2600, while a RAM (Random Access Memory) 2602 stores received data. The CPU 2600 processes the received data in accordance with a program that is stored in the ROM 2601. A radio receiving section 2608 obtains a received radio signal from the antenna 2607, and demodulates the radio signal to obtain a digital signal. A bit synchronization section 2603 achieves bit synchronization between the data conveyed by that digital signal and a reference clock signal, and uses that clock signal to sample the digital signal and recover the originally transmitted digital data. A de-interleaving section 2604 analyzes the received digital data, to convert the data back to de-interleaved form, and an address verification section 2605 examines data of successive received addresses contained in the digital data, to detect coincidence with an address which has been assigned to the paging receiver and is held in the ROM 2601. A data decoding section 2606 executes decoding of the BCH code of the de-interleaved received data, to effect error correction. A LCD driver 2609, in response to output signals from the CPU 2600, drives a LCD (liquid crystal display device) 2610, while an audio driver 2611 drives a loudspeaker (i.e. an electro-acoustic transducer device) 2612.
The operation of this paging receiver example is as follows. The antenna 2607 receives radio waves transmitted from a base station of the paging system, and converts these to an analog signal. The receiver section 2608 demodulates this analog signal to obtain a digital signal, which is supplied to the bit synchronization section 2603. The bit synchronization section 2603 establishes synchronization between a reference clock signal and the digital signal from the receiver section 2608, converts the received digital signal to the original digital data stream, which is supplied to the de-interleaving section 2604. The de-interleaving section 2604 executes de-interleaving processing of the received digital data, and supplies the resultant digital data to the address verification section 2605 and data decoding section 2606. The address verification section 2605 compares address portions within the received data with the address that has been assigned to that paging receiver, and when address coincidence is detected, the data decoding section 2606 executes decoding of the BCH code of the received digital data portion corresponding to that received address, to thereby perform error correction processing of that digital data portion and recover corrected data as a received message. The received message is then supplied to the CPU 2600.
The CPU 2600 first temporarily stores successive parts of the received message within the RAM 2602. When storing of the received message has been completed, it is supplied via the LCD driver section 2609 to be displayed by the LCD 2610. In addition, an indication signal is transferred via the audio driver section 2611 to activate the loudspeaker 2612 and generate an audible indication to the user that a message has been received.
It can thus be understood that with such a prior art type of paging receiver, it is necessary to utilize dedicated hardware apparatus units (i.e. the data decoding section 2606, address verification section 2605, and de-interleaving section 2604) to provide a de-interleaving function and a BCH decoding function for processing the received digital data. Patents relating to such a prior art method are for example U.S. Pat. No. 5,311,516 and Japanese Patent SHO 63-87031.
The most attractive features of a paging receiver, for the general user, are that the paging receiver be highly portable, have low utilization costs, and above all, that the paging receiver have a low purchase price. However if such prior art technology is used, it becomes necessary to incorporate special dedicated hardware for use in protocol analysis, i.e. de-interleaving and error correction processing. Furthermore, if the communication protocol is complex, then the hardware that is required for analyzing the protocol will become accordingly complex, with a resultant increase in the manufacturing cost of the paging receiver.
With the second approach on the other hand, i.e. the "software approach", it has been necessary in the prior art for the CPU to execute complex processing to analyze the communication protocol, so that this again will result in the need to utilize a sophisticated design for the CPU, resulting in a corresponding increase in the manufacturing cost of the paging receiver. Specifically, if the CPU must execute de-interleaving of the received digital data, followed by BCH decoding processing, then if for example BCH (31, 21) decoding processing must be executed, 31 bits of BCH code must be operated on by an 11-bit value which represents the set of coefficients of a predetermined polynomial, used to generate the BCH code. Specifically, modulo-2 division of the 31 BCH code bits by the 11-bit set of coefficients of the polynomial (generally referred to as the generator polynomial) is performed, i.e. a long-division operation in which a succession of exclusive-OR operations is performed to obtain respective intermediate values, and finally obtain a remainder, i.e. the error syndrome. However a practical type of paging receiver is in general limited to using an 8 bit CPU, i.e. a CPU which operates with a word length of 8 bits, and the processing performance is not very high. Moreover in order to reduce power consumption and to minimize radio interference, the CPU is limited to operating at a low value of clock frequency, i.e. only a low frequency of performing processing operations can be achieved. In particular, executing BCH decoding processing would place an excessive burden on such an 8-bit CPU. It would of course be possible to instead use a CPU which operates at a high clock rate, however this would result in an increase in radio interference that is generated by the CPU operation, causing a resultant lowering of the receiver sensitivity, so that this would result in other problems.
Moreover with such a "software approach", due to the load imposed on the CPU becoming excessive, the performance of the paging receiver will deteriorate. Specifically, while the paging receiver is executing receiving processing, the response to actuations of switches of the paging receiver by the user will become extremely slow. This is due to the fact that it is difficult to execute the various types of processing that are required in response to switch actuations concurrently with executing the processing that is necessary for communication protocol analysis.
It can thus be understood that in the prior art there are severe problems with regard to providing a paging receiver which can receive large amounts of data at a time, i.e. can receive data which are sent at a substantially higher transmission rate than has been possible with prior art types of paging receiver. These problems basically result from the difficulty of using a simple and inexpensive type of CPU (in general, an 8-bit CPU) which must be operated at a low clock frequency, for analyzing a data transfer protocol which employs interleaving and a complex error-correction encoding technique such as BCH encoding.